Invention Grant
- Patent Title: Analog multiplexer core circuit and analog multiplexer circuit
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Application No.: US15747139Application Date: 2016-07-21
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Publication No.: US10425051B2Publication Date: 2019-09-24
- Inventor: Munehiko Nagatani , Hideyuki Nosaka
- Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
- Applicant Address: JP Tokyo
- Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
- Current Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Womble Bond Dickinson (US) LLP
- Priority: JP2015-145430 20150723
- International Application: PCT/JP2016/071385 WO 20160721
- International Announcement: WO2017/014262 WO 20170126
- Main IPC: H03F3/45
- IPC: H03F3/45 ; H03K17/62 ; H04L27/36 ; H03K19/013 ; H04B1/04

Abstract:
An analog multiplexer core circuit (120A) includes a differential pair (121) that includes two transistors (Q1, Q2), a differential pair (122) that includes two transistors (Q3, Q4), a differential pair (123) that includes two transistors (Q5, Q6), and a constant current source (124) that causes a current (IEE) to flow. This analog multiplexer core circuit (120A) time-multiplexes two analog signals (Ain1, Ain2) and outputs a time-multiplexed analog signal (Aout). Each emitter resistor (REA1, REA2, REA3, REA4) is connected to a corresponding one of the transistors (Q1, Q2, Q3, Q4). At this time, a relation of “REA·IEE≥the amplitude of an input analog signal” is satisfied. As a result, linearity of response can be ensured by expanding the linear response input range of the differential pairs (121, 122).
Public/Granted literature
- US20180219517A1 ANALOG MULTIPLEXER CORE CIRCUIT AND ANALOG MULTIPLEXER CIRCUIT Public/Granted day:2018-08-02
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