Invention Grant
- Patent Title: Semiconductor apparatus
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Application No.: US15496400Application Date: 2017-04-25
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Publication No.: US10425074B2Publication Date: 2019-09-24
- Inventor: Sakae Nakajima
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2016-136822 20160711
- Main IPC: H03K17/284
- IPC: H03K17/284 ; H03K17/082 ; H01L27/02 ; H01L27/092 ; H02H5/04 ; H03K17/22 ; H02H9/02 ; H02H3/08

Abstract:
There has been a problem in semiconductor apparatuses of related art in which a circuit operation cannot be returned after a reverse current occurred. In one embodiment, a semiconductor apparatus includes a timer block configured to count up a count value to a predetermined value in response to a control signal being enabled, the control signal instructing a power MOS transistor to be turned on, and a protection transistor including a drain connected to a gate of the power MOS transistor, a source and a back gate connected to a source of the power MOS transistor, and an epitaxial layer in which the power MOS transistor is formed, the epitaxial layer being supplied with a power supply voltage. The protection transistor short-circuits the source and gate of the power MOS transistor in response to an output voltage of the power MOS transistor meeting a predetermined condition and the count value reaching the predetermined value. The timer block resets the count value when the output voltage of the power MOS transistor no longer meets the predetermined condition.
Public/Granted literature
- US20180013414A1 SEMICONDUCTOR APPARATUS Public/Granted day:2018-01-11
Information query
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