Invention Grant
- Patent Title: Field programmable logic array
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Application No.: US15546694Application Date: 2015-01-28
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Publication No.: US10425081B2Publication Date: 2019-09-24
- Inventor: Teruaki Sakata , Tsutomu Yamada , Teppei Hirotsu
- Applicant: Hitachi, Ltd.
- Applicant Address: JP Tokyo
- Assignee: Hitachi, Ltd.
- Current Assignee: Hitachi, Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Crowell & Moring LLP
- International Application: PCT/JP2015/052258 WO 20150128
- International Announcement: WO2016/121015 WO 20160804
- Main IPC: G06F11/00
- IPC: G06F11/00 ; H03K19/177 ; G01R31/3185 ; G01R31/317 ; G06F11/10 ; G11C29/52 ; G11C29/12 ; G11C29/04

Abstract:
To realize control of a system for which a high level of safety is demanded by one SRAM-type FPGA, it is to eliminate a possibility that an undesirable control signal is output to the outside of the FPGA because of influence of failure by a soft error and the like and a problem. To solve this problem, there is provided a hard macro having fixed circuitry structure, programmable logic arranged via an interval close to the hard macro and having a changeable circuitry structure, and an I/F circuit which is provided inside the programmable logic and outputs a processing result in the programmable logic to the hard macro. It is a characteristic that the I/F circuit monitors soundness of the programmable logic and stops output of the processing result to be transmitted to the hard macro on the basis of a monitoring result.
Public/Granted literature
- US20180278254A1 Field Programmable Logic Array Public/Granted day:2018-09-27
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