Subsampling phase frequency detector for a divider-less phase-locked loop
Abstract:
The disclosed embodiments relate to a system that controls a phase-locked loop (PLL), eliminating harmonic locking issues during subsampling operation and achieving better noise performance. During operation, the system performs a procedure to measure a first duty cycle that indicates a relationship between a reference signal, which has a frequency FREF, and a voltage-controlled oscillator (VCO) output signal, which has a frequency FVCO and is generated by a VCO. The system also performs the procedure to measure a second duty cycle that indicates a relationship between a second reference signal (with a frequency of c*FREF) and the VCO-output signal. Next, the system determines a frequency and phase relationship between the reference signal and the VCO-output signal based on the first and second duty cycles. Finally, the system uses the frequency and phase relationship to adjust the VCO so that the VCO-output signal, which is used as an output of the PLL, is frequency and phase aligned with the reference signal.
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