Invention Grant
- Patent Title: Subsampling phase frequency detector for a divider-less phase-locked loop
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Application No.: US15647716Application Date: 2017-07-12
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Publication No.: US10425092B2Publication Date: 2019-09-24
- Inventor: Guanghua Shu , Frankie Y. Liu
- Applicant: Oracle International Corporation
- Applicant Address: US CA Redwood Shores
- Assignee: Oracle International Corporation
- Current Assignee: Oracle International Corporation
- Current Assignee Address: US CA Redwood Shores
- Agency: Park, Vaughan, Fleming & Dowler LLP
- Main IPC: H03L7/20
- IPC: H03L7/20 ; H03L7/08

Abstract:
The disclosed embodiments relate to a system that controls a phase-locked loop (PLL), eliminating harmonic locking issues during subsampling operation and achieving better noise performance. During operation, the system performs a procedure to measure a first duty cycle that indicates a relationship between a reference signal, which has a frequency FREF, and a voltage-controlled oscillator (VCO) output signal, which has a frequency FVCO and is generated by a VCO. The system also performs the procedure to measure a second duty cycle that indicates a relationship between a second reference signal (with a frequency of c*FREF) and the VCO-output signal. Next, the system determines a frequency and phase relationship between the reference signal and the VCO-output signal based on the first and second duty cycles. Finally, the system uses the frequency and phase relationship to adjust the VCO so that the VCO-output signal, which is used as an output of the PLL, is frequency and phase aligned with the reference signal.
Public/Granted literature
- US20190020350A1 SUBSAMPLING PHASE FREQUENCY DETECTOR FOR A DIVIDER-LESS PHASE-LOCKED LOOP Public/Granted day:2019-01-17
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