- Patent Title: Monitoring correctable errors on a bus interface to determine whether to redirect input/output (I/O) traffic from a first processing unit to a second processing unit
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Application No.: US15612791Application Date: 2017-06-02
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Publication No.: US10430264B2Publication Date: 2019-10-01
- Inventor: Matthew G. Borlick , Lokesh M. Gupta , Trung N. Nguyen
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Konrad, Haynes, Davda and Victor LLP
- Agent David W. Victor
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/07

Abstract:
Provided are a computer program product for managing bus interface errors in a storage system coupled to a host and storage. A determination is made as to whether a first number of correctable errors on a first bus interface, connecting a first processing unit to the storage, exceeds a second number of correctable errors on a second bus interface, connecting a second processing unit to the storage, by a difference threshold. The correctable errors in the first and second bus interfaces are detected and corrected in the first and second bus interfaces by first hardware and second hardware, respectively. In response to determining that the first number of correctable errors exceeds the second number of correctable errors by the difference threshold, at least a portion of Input/Output (I/O) requests are redirected to a second processing unit using the second bus interface to connect to the storage.
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