Invention Grant
- Patent Title: Representing a cache line bit pattern via meta signaling
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Application No.: US15388752Application Date: 2016-12-22
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Publication No.: US10430335B2Publication Date: 2019-10-01
- Inventor: Saher Abu Rahme , Christopher E. Cox , Joydeep Ray
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/0804 ; G06F1/3225 ; G06F3/06 ; G06F12/0897 ; G06F12/0868
Abstract:
A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.
Public/Granted literature
- US20170103019A1 REPRESENTING A CACHE LINE BIT PATTERN VIA META SIGNALING Public/Granted day:2017-04-13
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