An information processing apparatus includes a memory and a processor: where the memory stores first correspondence information in which, regarding each of regions delimited based on a level of possibility that a path included in a circuit does not meet timing constraints, region information representing the region and a range of a value of an item relating to delay of the path are associated with each other and second correspondence information in which, regarding a certain region, region information that represents the certain region and countermeasure information that represents a countermeasure against delay of the path whose value of the item corresponds to the certain region are associated with each other; and the processor outputs the countermeasure information by referring to the first and the second correspondence information, regarding a value of the item relating to delay of a path included in a target circuit of verification.