Invention Grant
- Patent Title: Matrix reduction for lithography simulation
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Application No.: US14506644Application Date: 2014-10-04
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Publication No.: US10430543B2Publication Date: 2019-10-01
- Inventor: Thomas Christopher Cecil
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Alston & Bird LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G03F7/20

Abstract:
A matrix is produced for a semiconductor design. Interactions between mask edges in forming semiconductor shapes are determined and a graph created that shows those interactions. The graph is then partitioned into groups using a coloring algorithm, with each group representing one or more non-interacting mask edges. A lithography simulation is performed for each group, with the edges of that group perturbed, but the edges of other groups unmoved. The partial derivatives are calculated for the edges of a group based on the simulation with those edges perturbed, and used to populate locations in a Jacobian matrix. The Jacobian matrix is then used to solve an Optical Proximity Correction (OPC) problem by finding a mask edge correction vector for a given wafer targeting error vector.
Public/Granted literature
- US20160098511A1 MATRIX REDUCTION FOR LITHOGRAPHY SIMULATION Public/Granted day:2016-04-07
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