Invention Grant
- Patent Title: Multi-patterning graph reduction and checking flow method
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Application No.: US15255489Application Date: 2016-09-02
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Publication No.: US10430544B2Publication Date: 2019-10-01
- Inventor: Nien-Yu Tsai , Chin-Chang Hsu , Wen-Ju Preet Yang , Hsien-Hsin Sean Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G03F1/36

Abstract:
A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.
Public/Granted literature
- US20180068049A1 MULTI-PATTERNING GRAPH REDUCTION AND CHECKING FLOW METHOD Public/Granted day:2018-03-08
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