Invention Grant
- Patent Title: Pixel compression mechanism
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Application No.: US15710828Application Date: 2017-09-20
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Publication No.: US10430990B2Publication Date: 2019-10-01
- Inventor: Subramaniam Maiyuran , Jorge Garcia Pabon , Vasanth Ranganathan , Saikat Mandal , Karol Szerszen , Luis Cruz Camacho , Abhishek R. Appu , Joydeep Ray
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06T15/00
- IPC: G06T15/00 ; G06T15/40 ; G06T1/20 ; G09G5/00 ; G06T9/00

Abstract:
An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.
Public/Granted literature
- US20190087999A1 PIXEL COMPRESSION MECHANISM Public/Granted day:2019-03-21
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T15/00 | 3D〔三维〕图像的加工 |