A semiconductor memory device includes a plurality of banks each having a dedicated line and sharing a global line, a plurality of sub-global lines shared by neighboring banks among the plurality of banks, a plurality of data input/output circuits coupled to the plurality of banks, respectively, through the dedicated line and coupling the dedicated lines of corresponding banks to the sub-global lines in response to bank strobe signals, respectively, and a plurality of data intervention blocks corresponding to the plurality of sub-global lines, respectively, and coupling the global line to corresponding sub-global lines in response to a delayed write strobe signal or read strobe signals.