Invention Grant
- Patent Title: Semiconductor memory device including a memory cell with first and second transistors
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Application No.: US15705864Application Date: 2017-09-15
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Publication No.: US10431287B2Publication Date: 2019-10-01
- Inventor: Chika Tanaka , Keiji Ikeda
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2017-054791 20170321
- Main IPC: G11C11/404
- IPC: G11C11/404 ; G11C11/4096 ; G06N3/04 ; H01L27/12 ; H01L27/108 ; G11C11/56 ; G11C7/10 ; G11C11/4091 ; G11C11/54

Abstract:
According to one embodiment, a semiconductor memory device includes a memory cell including a transistor formed of an oxide semiconductor, an insulation film, and a control electrode, and a capacitance element configured to store a charge, the memory cell being configured to store a coupling weight of a neuron model by a charge amount accumulated in the capacitance element; and a control circuit configured to output a signal as a sum of a product between input data of the memory cell and the coupling weight.
Public/Granted literature
- US20180277192A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2018-09-27
Information query
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