An array organization and architecture for a content addressable memory (CAM) system. More specifically, a circuit is provided for that includes a first portion of the CAM configured to perform a first inequality operation implemented between 1 to n CAM entries. The circuit further includes a second portion of the CAM configured to perform a second inequality operation implemented between the 1 to n CAM entries. The first portion and the second portion are triangularly arranged side by side such that the first inequality operation and the second inequality operation are implemented between the 1 to n CAM entries using the same n wordlines.