Invention Grant
- Patent Title: Embedded transconductance test circuit and method for flash memory cells
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Application No.: US16019135Application Date: 2018-06-26
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Publication No.: US10431321B1Publication Date: 2019-10-01
- Inventor: Sung Jin Yoo
- Applicant: Integrated Silicon Solution, (Cayman) Inc.
- Applicant Address: KY Grand Cayman
- Assignee: Integrated Silicon Solutions, (Cayman) Inc.
- Current Assignee: Integrated Silicon Solutions, (Cayman) Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Patent Law Works LLP
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C29/50 ; G11C16/14

Abstract:
A transconductance test method implemented in a flash memory device detects memory cells with low transconductance and provides an output identifying memory cells, if any, having been classified as having a low transconductance (low gm). In some embodiments, the transconductance test method implements multi-step testing using a pair of gate bias levels for each test step. Accurate detection of memory cells with low transconductance can be realized.
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