Invention Grant
- Patent Title: Calibrating I/O impedances using estimation of memory die temperature
-
Application No.: US16056682Application Date: 2018-08-07
-
Publication No.: US10431323B2Publication Date: 2019-10-01
- Inventor: Jason Griffin
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Agency: White & Case LLP
- Main IPC: G11C7/04
- IPC: G11C7/04 ; G11C29/50 ; G06F13/40 ; G11C29/02 ; G11C29/46 ; G11C11/406 ; G11C11/4076 ; G06F13/16 ; G11C29/52

Abstract:
A memory system includes a calibration engine, a memory, and a memory controller coupled to the memory by a channel used to transmit a plurality of commands from the memory controller to the memory. The memory controller estimates a total energy consumed based on the first plurality of commands in a first sampling period and determines a first temperature change of the memory based on the first total energy consumed. The memory controller transmits an impedance calibration command to the calibration engine if the first temperature change of the memory exceeds a first threshold. The calibration engine changes an impedance of an I/O terminal of the memory based on the calibration command.
Public/Granted literature
- US20180342309A1 CALIBRATING I/O IMPEDANCES USING ESTIMATION OF MEMORY DIE TEMPERATURE Public/Granted day:2018-11-29
Information query