Invention Grant
- Patent Title: Memory cell, semiconductor integrated circuit device, and method for manufacturing semiconductor integrated circuit device
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Application No.: US15744163Application Date: 2016-07-21
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Publication No.: US10431589B2Publication Date: 2019-10-01
- Inventor: Shoji Yoshida , Fukuo Owada , Daisuke Okada , Yasuhiko Kawashima , Shinji Yoshida , Kazumasa Yanagisawa , Yasuhiro Taniguchi
- Applicant: FLOADIA CORPORATION
- Applicant Address: JP Tokyo
- Assignee: FLOADIA CORPORATION
- Current Assignee: FLOADIA CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Pearne & Gordon LLP
- Priority: JP2015-146189 20150723
- International Application: PCT/JP2016/071351 WO 20160721
- International Announcement: WO2017/014254 WO 20170126
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L29/788 ; H01L29/792 ; H01L21/28 ; H01L27/10 ; H01L29/423 ; H01L29/66 ; H01L27/1157 ; H01L27/11573 ; H01L27/11575

Abstract:
A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.
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