Invention Grant
- Patent Title: Apparatuses and methods for semiconductor circuit layout
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Application No.: US15967219Application Date: 2018-04-30
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Publication No.: US10431647B2Publication Date: 2019-10-01
- Inventor: Harunobu Kondo , Kenichi Echigoya
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L23/528 ; H01L23/522 ; H01L49/02 ; H01L27/08

Abstract:
Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the first, second and third capacitors including first and second electrodes. The first electrodes of the first, second and third capacitors are electrically coupled in common to one another. The second electrodes of the first and third capacitors are electrically coupled in common to each other. The second electrode of the second capacitor is electrically insulated from the second electrodes of the first and third capacitors.
Public/Granted literature
- US20180247998A1 APPARATUSES AND METHODS FOR SEMICONDUCTOR CIRCUIT LAYOUT Public/Granted day:2018-08-30
Information query
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