- Patent Title: Integrated circuit (IC) employing a channel structure layout having an active semiconductor channel structure(s) and an isolated neighboring dummy semiconductor channel structure(s) for increased uniformity
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Application No.: US16126886Application Date: 2018-09-10
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Publication No.: US10431686B1Publication Date: 2019-10-01
- Inventor: Haining Yang , Xiangdong Chen
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: W&T/Qualcomm
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/8234 ; H01L27/088 ; H01L29/66

Abstract:
An integrated circuit (IC) employs a channel structure layout having an active semiconductor channel structure(s) and an isolated neighboring dummy semiconductor channel structure(s) for increased uniformity. A semiconductor channel structure(s) in an IC is a fin structure(s) or a gate-all-around (GAA) structure(s) employed in a Field-Effect Transistor (FET), such as a FinFET or a three-dimensional (3D) FET. The channel structures in the IC are fabricated according to a circuit cell architecture, such as a standard circuit cell (“standard cell”). The IC includes an active (e.g., diffusion) region in which a semiconductor channel structure array (e.g., semiconductor fin array) is formed according to a pattern. The IC includes a device employing a channel structure array in the active region. The channel structure array may include one active channel structure (e.g., fin) for reduced power consumption in the FinFET, and may include at least one dummy fin for increased uniformity.
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