An integrated circuit comprises an ADC including a first track-and-hold amplifier and a timing generator configured to generate a clock signal for controlling the ADC. The timing generator comprises a quadrature filter responsive to a differential input signal for generating a differential quadrature (I/Q) output signal. The timing generator further comprises at least one first vector sum circuit operatively coupled or connected to an output of the quadrature filter and configured to weight and sum components of the differential I/Q output signal for generating a clock signal having a desired delay.