Invention Grant
- Patent Title: Automated semiconductor platform testing
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Application No.: US15467532Application Date: 2017-03-23
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Publication No.: US10436838B2Publication Date: 2019-10-08
- Inventor: Sneha S. Pingle , Soumya P. Mukherjee , Chandrashekhar Mutuguppe Venkataramana , Divya Appaji Lalithamba
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Grossman, Tucker, Perreault & Pfleger, PLLC
- Main IPC: G01R31/3183
- IPC: G01R31/3183 ; G11C29/38 ; G11C29/36 ; G06N20/00 ; G11C29/56

Abstract:
The present disclosure is directed to systems and methods for autonomously generating test methods for testing features included on semiconductor platforms. The systems and methods described herein either manually or autonomously receive information and/or data indicative of the features included in, on, or about a semiconductor platform to be tested. Based on the presence of features and/or feature combinations on the semiconductor platform, the systems and methods described herein autonomously select the appropriate test blocks used to generate the test method. The systems and methods described herein generate additional test methods as permutations of the selected test blocks. The validity of each test method is confirmed using dependency rules and all valid test methods are combined to form a test package that is used to test the semiconductor platform.
Public/Granted literature
- US20180277235A1 AUTOMATED SEMICONDUCTOR PLATFORM TESTING Public/Granted day:2018-09-27
Information query
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