Scheduling events in hardware design language simulation
Abstract:
Simulating a circuit design can include detecting, using a processor, an assignment for a signal of a circuit design during a delta cycle of a simulation of the circuit design and comparing, using the processor, a range of the assignment for the signal with a range of an existing event for the signal for the delta cycle. In response to determining that the range of the assignment for the signal and the range of the existing event meet a condition, the existing event is updated, using the processor, resulting in a merged event. The merged event is scheduled for execution for the delta cycle using the processor.
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