Invention Grant
- Patent Title: Scheduling events in hardware design language simulation
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Application No.: US15676104Application Date: 2017-08-14
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Publication No.: US10437949B1Publication Date: 2019-10-08
- Inventor: Valeria Mihalache , Kumar Deepak , Saikat Bandyopadhyay
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent Kevin T. Cuenot
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50

Abstract:
Simulating a circuit design can include detecting, using a processor, an assignment for a signal of a circuit design during a delta cycle of a simulation of the circuit design and comparing, using the processor, a range of the assignment for the signal with a range of an existing event for the signal for the delta cycle. In response to determining that the range of the assignment for the signal and the range of the existing event meet a condition, the existing event is updated, using the processor, resulting in a merged event. The merged event is scheduled for execution for the delta cycle using the processor.
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