Invention Grant
- Patent Title: Two-pass cache tile processing for visibility testing in a tile-based architecture
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Application No.: US15960332Application Date: 2018-04-23
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Publication No.: US10438314B2Publication Date: 2019-10-08
- Inventor: Ziyad S. Hakura , Jerome F. Duluk, Jr.
- Applicant: NVIDIA Corporation
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORPORATION
- Current Assignee: NVIDIA CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: G06T1/20
- IPC: G06T1/20 ; G06T15/00 ; G06T15/40 ; G06F9/38 ; G06T1/60 ; G06F12/0875 ; G06F9/44 ; G06T17/20 ; G09G5/395 ; G09G5/00 ; G06T15/50 ; G06F12/0808 ; G06T15/80

Abstract:
One embodiment of the present invention sets forth a graphics processing system. The graphics processing system includes a screen-space pipeline and a tiling unit. The screen-space pipeline is configured to perform visibility testing and fragment shading. The tiling unit is configured to determine that a first set of primitives overlaps a first cache tile. The tiling unit is also configured to first transmit the first set of primitives to the screen-space pipeline with a command configured to cause the screen-space pipeline to process the first set of primitives in a z-only mode, and then transmit the first set of primitives to the screen-space pipeline with a command configured to cause the screen-space pipeline to process the first set of primitives in a normal mode. In the z-only mode, at least some fragment shading operations are disabled in the screen-space pipeline. In the normal mode, fragment shading operations are enabled.
Public/Granted literature
- US20190243652A9 TWO-PASS CACHE TILE PROCESSING FOR VISIBILITY TESTING IN A TILE-BASED ARCHITECTURE Public/Granted day:2019-08-08
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