Invention Grant
- Patent Title: Test structures and test pads in scribe lane of semiconductor integrated circuit
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Application No.: US15840651Application Date: 2017-12-13
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Publication No.: US10438681B2Publication Date: 2019-10-08
- Inventor: Kwi Dong Kim
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si, Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si, Gyeonggi-do
- Agency: William Park & Associates Ltd.
- Priority: KR10-2017-0044385 20170405
- Main IPC: G11C29/38
- IPC: G11C29/38 ; H01L27/115 ; G11C29/12 ; G11C29/48 ; H01L21/66 ; H01L23/544 ; H01L27/112
Abstract:
A semiconductor integrated circuit device may include a plurality of semiconductor chips, a scribe lane, connecting wiring, and a selection circuit. Each of the semiconductor chips may include a peripheral circuit. The scribe lane may be positioned between the semiconductor chips. A test pad may be arranged in the scribe lane. The connecting wiring may be connected between the test pad and the peripheral circuit. The selection circuit may be configured to selectively connect or disconnect the connecting wiring.
Public/Granted literature
- US20180294043A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING TEST PADS Public/Granted day:2018-10-11
Information query
