Invention Grant
- Patent Title: Selective planishing method for making a semiconductor device
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Application No.: US15913499Application Date: 2018-03-06
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Publication No.: US10438816B2Publication Date: 2019-10-08
- Inventor: Donald C. Abbott
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Rose Alyssa Keagy; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L21/56 ; H01L21/64 ; H01L23/495 ; H01L23/00
Abstract:
In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.
Public/Granted literature
- US20180204739A1 SELECTIVE PLANISHING METHOD FOR MAKING A SEMICONDUCTOR DEVICE Public/Granted day:2018-07-19
Information query
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