Invention Grant
- Patent Title: Semiconductor structure and related method
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Application No.: US15621563Application Date: 2017-06-13
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Publication No.: US10438838B2Publication Date: 2019-10-08
- Inventor: Yu-Hsiang Tsai , Chung-Chuan Tseng , Li Hsin Chu , Chia-Wei Liu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L29/06 ; H01L21/78 ; H01L21/762 ; H01L21/84 ; H01L21/02

Abstract:
A method and structure for providing a semiconductor-on-insulator (SCOI) wafer having a buried low-K dielectric layer includes forming a device layer on a first semiconductor substrate. In various embodiments, at least a portion of the device layer is separated from the first semiconductor substrate, where the separating forms a cleaved surface on the separated portion of the device layer. In some examples, a patterned low-K dielectric layer is formed on a second semiconductor substrate. Thereafter, and in some embodiments, the separated portion of the device layer is bonded, along the cleaved surface, to the patterned low-K dielectric layer.
Public/Granted literature
- US20180061698A1 Semiconductor Structure and Related Method Public/Granted day:2018-03-01
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