Invention Grant
- Patent Title: Method for manufacturing CMOS structure
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Application No.: US15995330Application Date: 2018-06-01
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Publication No.: US10438854B2Publication Date: 2019-10-08
- Inventor: Budong You , Zheng Lyu , Xianguo Huang , Chuan Peng
- Applicant: Silergy Semiconductor Technology (Hangzhou) LTD
- Applicant Address: CN Hangzhou
- Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
- Current Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
- Current Assignee Address: CN Hangzhou
- Agent Michael C. Stephens, Jr.
- Priority: CN201410392572 20140811; CN201410456374 20140909
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H01L21/265 ; H01L29/66 ; H01L21/8238

Abstract:
The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type.
Public/Granted literature
- US20180277447A1 METHOD FOR MANUFACTURING CMOS STRUCTURE Public/Granted day:2018-09-27
Information query
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