Invention Grant
- Patent Title: Integrally formed bias and signal lead for a packaged transistor device
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Application No.: US15787903Application Date: 2017-10-19
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Publication No.: US10438908B2Publication Date: 2019-10-08
- Inventor: Arturo Roiz , Justin Nelson Annes , Terry L. Thomas
- Applicant: NXP USA, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H01L23/66
- IPC: H01L23/66 ; H01L23/047 ; H01L23/22 ; H01L23/00
Abstract:
A lead, for a packaged transistor device, having a signal portion and a bias line portion, with the signal portion and the bias line portion each having a proximal end and a distal end. The signal portion and the bias line portions of the lead are integrally formed together as a single conductive component, with the proximal end of the bias line portion integrated into the signal portion of the lead and with the distal ends of the signal portion and the bias line portion physically separate from each other.
Public/Granted literature
- US20190123002A1 INTEGRALLY FORMED BIAS AND SIGNAL LEAD FOR A PACKAGED TRANSISTOR DEVICE Public/Granted day:2019-04-25
Information query
IPC分类:
