- Patent Title: Semiconductor memory device and method of manufacturing the same
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Application No.: US15692343Application Date: 2017-08-31
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Publication No.: US10439002B2Publication Date: 2019-10-08
- Inventor: Kenichi Murooka
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L27/24
- IPC: H01L27/24 ; H01L27/105 ; H01L45/00 ; G11C13/00

Abstract:
A connection unit is provided adjacently to the cell array unit and electrically connected to a peripheral circuit unit positioned downwardly of the cell array unit. The cell array unit has a configuration in which a variable resistance layer is provided at intersections of a plurality of word lines extending in a horizontal direction and a plurality of bit lines extending in a vertical direction. The connection unit includes a lower wiring line layer in which a base portion bundling a plurality of the word lines is formed, and a middle wiring line layer and upper wiring line layer formed upwardly thereof. The lower wiring line layer includes: a first penetrating electrode connecting the plurality of word lines and the peripheral circuit unit; and a second penetrating electrode connecting at least one of the middle wiring line layer and upper wiring line layer and the peripheral circuit unit.
Public/Granted literature
- US20170365639A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2017-12-21
Information query
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