Invention Grant
- Patent Title: Integrated circuit with triple guard wall pocket isolation
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Application No.: US15180592Application Date: 2016-06-13
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Publication No.: US10439024B2Publication Date: 2019-10-08
- Inventor: Karim-Thomas Taghizadeh Kaschani , Antonio Gallerano
- Applicant: Texas Instruments Incorporated , Texas Instruments Deutschland GmbH
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L29/06

Abstract:
A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.
Public/Granted literature
- US20170358570A1 INTEGRATED CIRCUIT WITH TRIPLE GUARD WALL POCKET ISOLATION Public/Granted day:2017-12-14
Information query
IPC分类: