A semiconductor device may include a latch circuit configured for storing a row address including information on a position where a smart refresh operation has been performed, as a storage address. The semiconductor device may include a refresh control circuit configured for controlling, depending on a result of comparing a row address inputted from an exterior and the storage address, a smart refresh operation to be performed for the row address, and omitting the smart refresh operation based on the row address and the storage address being the same combination.