A memory device includes first and second resistance change elements and first and second double-gate transistors. The first resistance change element includes first and second terminals. The second resistance change element includes a third terminal coupled to the first terminal and a fourth terminal. The first double-gate transistor includes a fifth terminal coupled to the second terminal, a sixth terminal, and a first gate coupled to a first word line and a second gate coupled to a second word line. The second double-gate transistor includes a seventh terminal coupled to the fourth terminal, an eighth element, and a third gate coupled to the first word line and a fourth gate coupled to a third word line.