Vertical tunneling field effect transistor device and fabrication method thereof

Invention Grant

US10446660B2 Vertical tunneling field effect transistor device and fabrication method thereof 有权

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Patent Title: Vertical tunneling field effect transistor device and fabrication method thereof
Application No.: US15974426

Application Date: 2018-05-08
Publication No.: US10446660B2

Publication Date: 2019-10-15
Inventor: Yong Li
Applicant: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
Applicant Address: CN Shanghai CN Beijing
Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
Current Assignee Address: CN Shanghai CN Beijing
Agency: Anova Law Group, PLLC
Priority: CN201710323454 20170509
Main IPC: H01L21/8234
IPC: H01L21/8234 ; H01L29/66 ; G11C11/412 ; H01L29/423 ; H01L21/762 ; H01L29/78 ; B82Y10/00 ; H01L29/40 ; H01L29/06 ; H01L29/775

Vertical tunneling field effect transistor device and fabrication method thereof

Abstract:

A VTFET device and fabrication method is provided. The method includes: forming a first doped layer on a semiconductor substrate. Vertical nanowires are formed on the first doped layer. Dummy gate layers are formed on the first doped layer, and a first interlayer dielectric layer is formed on a top surface of the first doped layer exposed by dummy gate layers. Grooves are formed in the first interlayer dielectric layer, by removing a portion of the first interlayer dielectric layer and removing a partial thickness of the vertical nanowires. A second doped layer is formed in each groove. Openings are formed by etching the first interlayer dielectric layer between adjacent vertical nanowires, to expose the dummy gate layers. The dummy gate layers are removed through the openings to form cavities and each cavity includes the opening and a space provided by the removed dummy gate layers.

Public/Granted literature

US20180331202A1 VERTICAL TUNNELING FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF Public/Granted day:2018-11-15

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺