Invention Grant
- Patent Title: Method of semiconductor integrated circuit fabrication
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Application No.: US15953708Application Date: 2018-04-16
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Publication No.: US10453746B2Publication Date: 2019-10-22
- Inventor: Ching-Fu Yeh , Chao-Hsien Peng , Hsien-Chang Wu , Hsiang-Huan Lee
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/768 ; H01L21/02 ; H01L23/532 ; H01L21/027 ; H01L21/3213 ; B82Y40/00

Abstract:
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
Public/Granted literature
- US20180233406A1 Method of Semiconductor Integrated Circuit Fabrication Public/Granted day:2018-08-16
Information query
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