Invention Grant
- Patent Title: Method and apparatus for forming multi-layered vias in sequentially fabricated circuits
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Application No.: US15160303Application Date: 2016-05-20
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Publication No.: US10453787B2Publication Date: 2019-10-22
- Inventor: Maurice S. Karpman , Nicole S. Mueller , Gary B. Tepolt , Russell Berman
- Applicant: The Charles Stark Draper Laboratory, Inc.
- Applicant Address: US MA Cambridge
- Assignee: THE CHARLES STARK DRAPER LABORATORY, INC.
- Current Assignee: THE CHARLES STARK DRAPER LABORATORY, INC.
- Current Assignee Address: US MA Cambridge
- Agency: Womble Bond Dickinson (US) LLP
- Agent John J. Penny, Jr.
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/498 ; H05K1/02 ; H05K1/11 ; H05K3/00 ; H05K3/40 ; H05K3/46 ; H01L23/14 ; H01L23/522
Abstract:
An electronic module assembly including a via spanning multiple layers in a wafer based module is described. The electronic module assembly can include a first layer deposited upon a substrate, a second layer deposited on a top surface of the first layer, and the via spanning multiple layers. The via can include a first bottom that is formed on a top surface of the first layer and a first sidewall that upstands from the first bottom and extending at least through the second layer.
Public/Granted literature
- US20160343652A1 METHOD AND APPARATUS FOR FORMING MULTI-LAYERED VIAS IN SEQUENTIALLY FABRICATED CIRCUITS Public/Granted day:2016-11-24
Information query
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