Invention Grant
- Patent Title: Using three or more masks to define contact-line-blocking components in FinFET SRAM fabrication
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Application No.: US16206539Application Date: 2018-11-30
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Publication No.: US10453852B2Publication Date: 2019-10-22
- Inventor: Shih-Han Huang , Chih-Hung Hsieh
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L27/11
- IPC: H01L27/11 ; H01L21/02 ; H01L21/265 ; H01L21/311 ; H01L21/768 ; H01L21/8238 ; H01L27/092 ; H01L29/78

Abstract:
A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device.
Public/Granted literature
- US20190109142A1 Using Three or More Masks to Define Contact-Line-Blocking Components in FinFET SRAM Fabrication Public/Granted day:2019-04-11
Information query
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