Invention Grant
- Patent Title: Latch circuit and comparator circuit
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Application No.: US15695938Application Date: 2017-09-05
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Publication No.: US10454458B2Publication Date: 2019-10-22
- Inventor: Masayuki Usuda
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Foley & Lardner LLP
- Priority: JP2017-047689 20170313
- Main IPC: H03K3/2885
- IPC: H03K3/2885 ; H03K3/012 ; H03K3/037 ; H03K3/356
Abstract:
A latch circuit includes first and second NAND circuits and first and second capacitive elements. The first NAND circuit has a first input node into which a first signal is input. The second NAND circuit has a first input node into which a second signal is input, a second input node which is connected to an output node of the first NAND circuit, and an output node which is connected to a second input node of the first NAND circuit. The first capacitive element has one end connected to the first input node of the first NAND circuit and has another end connected to the output node of the first NAND circuit. The second capacitive element has one end connected to the first input node of the second NAND circuit and has another end connected to the output node of the second NAND circuit.
Public/Granted literature
- US20180262182A1 LATCH CIRCUIT AND COMPARATOR CIRCUIT Public/Granted day:2018-09-13
Information query
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