Systems and methods for processing and arbitrating submission and completion queues are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device processes the commands through various phases including fetching, processing, posting a completion message, and sending an interrupt to the host. The memory device may process the commands based on the determined priority of the command. For example, the memory device may determine a priority for performing the phases after fetching the command. As another example, the memory device may perform the internal command selection based on a priority associated with the command. In this way, commands may be executed based on the priority needs of the memory device or of the host device.