Disclosed is a display driving device capable of reducing an output response delay of an output buffer. The display driving device may include: a first DAC configured to load a first grayscale voltage corresponding to first digital data as a first DAC signal; a second DAC configured to load a second grayscale voltage corresponding to second digital data as a second DAC signal; and an output buffer configured to alternately select the first DAC signal loaded to a first input terminal and the second DAC signal loaded to a second input terminal.