A memory system is provided. The memory system includes a memory device and a memory controller. The memory device includes a plurality of memory dies and a refresh controller, and the refresh controller includes a refresh skip control block. The memory controller transmits a refresh skip period signal of each of the memory dies to the refresh skip control block according to a result of an error correction code (ECC) decoding operation performed on each of the memory dies so that the memory dies have independent refresh skip periods.