Invention Grant
- Patent Title: Integrated circuit devices including separate memory cells on separate regions of individual substrate
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Application No.: US15826031Application Date: 2017-11-29
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Publication No.: US10468103B2Publication Date: 2019-11-05
- Inventor: Sung-woo Kim , Jae-kyu Lee , Ki-seok Suh , Hyeong-sun Hong , Yoo-sang Hwang , Gwan-hyeob Koh
- Applicant: Sung-woo Kim , Jae-kyu Lee , Ki-seok Suh , Hyeong-sun Hong , Yoo-sang Hwang , Gwan-hyeob Koh
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2016-0162915 20161201
- Main IPC: G11C14/00
- IPC: G11C14/00 ; H01L45/00 ; H01L29/08 ; H01L27/108 ; H01L23/528 ; H01L29/423 ; H01L43/08 ; H01L43/02 ; H01L43/12 ; H01L27/24 ; H01L27/22 ; H01L27/105 ; H01L27/02 ; G11C7/10 ; G11C11/00

Abstract:
An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.
Public/Granted literature
- US20180158526A1 INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING SAME Public/Granted day:2018-06-07
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