Invention Grant
- Patent Title: Processor and control method of processor
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Application No.: US15897242Application Date: 2018-02-15
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Publication No.: US10468115B2Publication Date: 2019-11-05
- Inventor: Keisuke Nishida , Shiro Kamoshida
- Applicant: FUJITSU LIMITED
- Applicant Address: JP Kawasaki
- Assignee: FUJITSU LIMITED
- Current Assignee: FUJITSU LIMITED
- Current Assignee Address: JP Kawasaki
- Agency: Fujitsu Patent Center
- Priority: JP2017-040528 20170303
- Main IPC: G11C29/42
- IPC: G11C29/42 ; G06F11/10

Abstract:
A processor includes: an error checking and correcting information generating unit; a storage unit configured to store data to which error checking and correcting information and error uncorrectable information are added when an error is detected and configured to store data to which error checking and correcting information is added when an error is not detected; and a processing unit configured to read out all data which the storage unit stores and configured to check an error of each piece of read-out data based on error checking/correcting information added to each piece of all the read-out data when an arithmetic unit detects an error, and configured to correct data in which an error is detected based on error checking and correcting information when a correctable error is detected.
Public/Granted literature
- US20180253354A1 PROCESSOR AND CONTROL METHOD OF PROCESSOR Public/Granted day:2018-09-06
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