Invention Grant
- Patent Title: High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
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Application No.: US16077142Application Date: 2017-01-31
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Publication No.: US10468294B2Publication Date: 2019-11-05
- Inventor: Igor Peidous , Andrew M. Jones , Srikanth Kommu , Gang Wang , Jeffrey L. Libbert
- Applicant: SUNEDISON SEMICONDUCTOR LIMITED , Igor Peidous
- Applicant Address: TW Hsinchu
- Assignee: GlobalWafers Co., Ltd.
- Current Assignee: GlobalWafers Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Armstrong Teasdale LLP
- International Application: PCT/US2017/015813 WO 20170131
- International Announcement: WO2017/142704 WO 20170824
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L21/36 ; H01L21/30 ; H01L21/46 ; H01L29/04 ; H01L31/036 ; H01L21/762 ; H01L21/02 ; H01L21/28

Abstract:
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.
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