Invention Grant
- Patent Title: Apparatuses and methods for TSV resistance and short measurement in a stacked device
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Application No.: US15715504Application Date: 2017-09-26
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Publication No.: US10468313B2Publication Date: 2019-11-05
- Inventor: Naohisa Nishioka
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; G01R31/28 ; H01L21/66 ; H01L25/065 ; H01L25/00

Abstract:
Examples described herein include apparatuses and methods TSV resistance and short measurement in a stacked device. An example apparatus may include a chip comprising semiconductor substrate including a first surface and a second surface opposite to the first surface. The chip may include a first terminal formed above the first surface, a second terminal formed above the second surface, a buffer circuit coupled between the first and second terminals, a first through-substrate via (TSV) penetrating the semiconductor substrate, and a first switch coupled between the first terminal and the first TSV.
Public/Granted literature
- US20190096776A1 APPARATUSES AND METHODS FOR TSV RESISTANCE AND SHORT MEASUREMENT IN A STACKED DEVICE Public/Granted day:2019-03-28
Information query
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