Invention Grant
- Patent Title: Method for manufacturing interconnection
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Application No.: US15891394Application Date: 2018-02-08
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Publication No.: US10468348B2Publication Date: 2019-11-05
- Inventor: Che-Cheng Chang , Chih-Han Lin , Horng-Huei Tseng
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L23/528 ; H01L23/532 ; H01L29/06 ; H01L21/768

Abstract:
A method for manufacturing an interconnect structure is provided, and the method is as below. A dielectric layer is deposited over a substrate. The dielectric layer is etched to form a recess. A dummy adhesion layer is deposited on sidewalls of the recess. A conductive layer is formed in the recess. The dummy adhesion layer is removed to expose a portion of the conductive layer.
Public/Granted literature
- US20180174956A1 METHOD FOR MANUFACTURING INTERCONNECTION Public/Granted day:2018-06-21
Information query
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