Invention Grant
- Patent Title: Semiconductor device and method for manufacturing same
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Application No.: US15569283Application Date: 2016-04-19
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Publication No.: US10468533B2Publication Date: 2019-11-05
- Inventor: Hiroshi Aichi
- Applicant: SHARP KABUSHIKI KAISHA
- Applicant Address: JP Sakai, Osaka
- Assignee: SHARP KABUSHIKI KAISHA
- Current Assignee: SHARP KABUSHIKI KAISHA
- Current Assignee Address: JP Sakai, Osaka
- Agency: ScienBiziP, P.C.
- Priority: JP2015-091063 20150428
- International Application: PCT/JP2016/062369 WO 20160419
- International Announcement: WO2016/175086 WO 20161103
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L21/265 ; H01L21/266 ; H01L21/324 ; H01L27/12 ; H01L29/66

Abstract:
A semiconductor device includes at least one thin film transistor (100, 200), the at least one thin film transistor including a semiconductor layer (3A, 3B) which includes a channel region (31A, 31), a high-concentration impurity region, and a low-concentration impurity region (32A, 32B) which is located between the channel region and the high-concentration impurity region, a gate electrode (7A, 7B) provided on a gate insulating layer (5), an interlayer insulating layer (11) provided on the gate electrode, and a source electrode (8A, 8B) and a drain electrode (9A, 9B), wherein the interlayer insulating layer and the gate insulating layer have a contact hole extending to the semiconductor layer, at least one of the source electrode (8A, 8B) and the drain electrode (9A, 9B) being in contact with the high-concentration impurity region inside the contact hole, at a side wall of the contact hole, a side surface of the gate insulating layer is aligned with a side surface of the interlayer insulating layer, and at an upper surface of the semiconductor layer, an edge of the contact hole aligned with an edge of the high-concentration impurity region.
Public/Granted literature
- US20180122955A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME Public/Granted day:2018-05-03
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