Invention Grant
- Patent Title: Word-line pre-charging in power-on read operation to reduce programming voltage leakage
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Application No.: US15844037Application Date: 2017-12-15
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Publication No.: US10475493B2Publication Date: 2019-11-12
- Inventor: Manabu Sakai , Qui Vi Nguyen , Yen-Lung Li
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Plano
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Plano
- Agency: Foley & Lardner LLP
- Main IPC: G11C8/08
- IPC: G11C8/08 ; G11C16/08 ; G11C5/14 ; G11C16/26 ; G11C16/30 ; G11C16/04

Abstract:
This disclosure provides techniques for reducing leakage current in a non-volatile memory that does not include a local interconnect. In one example, a low-voltage pulse can be applied to all of the word-lines in all of the blocks of the non-volatile memory. The low-voltage pulse can be applied during a period in which the row decoder is typically idle in order to reduce the total amount of time required to program the non-volatile memory. After the conclusion low-voltage pulse, a global control line voltage can be applied at about the same level as the low-voltage pulse to keep the word-lines floating when the pulse is no longer applied.
Public/Granted literature
- US20190066789A1 WORD-LINE PRE-CHARGING IN POWER-ON READ OPERATION TO REDUCE PROGRAMMING VOLTAGE LEAKAGE Public/Granted day:2019-02-28
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