An equalizer circuit includes a first adder circuit adding an input signal and including an addition terminal and a subtraction terminal; a comparator circuit comparing an output signal of the first adder circuit; a latch circuit latching data output from the comparator circuit; a first digital/analog converter circuit which outputs a first signal corresponding to an absolute value of an equalizing coefficient, when the equalizing coefficient is a positive value; a second digital/analog converter circuit which outputs a second signal corresponding to an absolute value of the equalizing coefficient, when the equalizing coefficient is a negative value; and a switch circuit which switches a connection between a set of an output terminal of the first digital/analog converter circuit, an output terminal of the second digital/analog converter circuit, and a set of the addition terminal and the subtraction terminal, based on the data latched in the latch circuit.