Invention Grant
- Patent Title: Wafer level integration including design/co-design, structure process, equipment stress management and thermal management
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Application No.: US15272838Application Date: 2016-09-22
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Publication No.: US10483215B2Publication Date: 2019-11-19
- Inventor: Jeffrey Gelorme , Li-Wen Hung , John U. Knickerbocker
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Gibbons Gutman Bongini Bianco PL
- Agent Donna Flores
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L23/58
Abstract:
A multi-layer wafer and method of manufacturing such wafer are provided. The method includes applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.
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