Invention Grant
- Patent Title: Low voltage NPN with low trigger voltage and high snap back voltage for ESD protection
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Application No.: US14182937Application Date: 2014-02-18
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Publication No.: US10483257B2Publication Date: 2019-11-19
- Inventor: Chai Ean Gill , Changsoo Hong
- Applicant: Freescale Semiconductor, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L29/66 ; H01L29/735 ; H01L29/06 ; H01L29/08 ; H01L29/10 ; H01L21/762
Abstract:
An area-efficient, low voltage ESD protection device (200) is provided for protecting low voltage pins (229, 230) against ESD events by using one or more stacked low voltage NPN bipolar junction transistors, each formed in a p-type material with an N+ collector region (216) and P+ base region (218) formed on opposite sides of an N+ emitter region (217) with separate halo extension regions (220-222) formed around at least the collector and emitter regions to improve the second trigger or breakdown current (It2) and set the snapback voltage (Vsb) and triggering voltage (Vt1) at the desired level.
Public/Granted literature
- US20150236009A1 Low Voltage NPN with Low Trigger Voltage and High Snap Back Voltage for ESD Protection Public/Granted day:2015-08-20
Information query
IPC分类:
