Invention Grant
- Patent Title: Phase-locked loop, phase-locking method, and communication unit
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Application No.: US15751094Application Date: 2016-08-15
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Publication No.: US10483989B2Publication Date: 2019-11-19
- Inventor: Takashi Masuda
- Applicant: Sony Semiconductor Solutions Corporation
- Applicant Address: JP Kanagawa
- Assignee: Sony Semiconductor Solutions Corporation
- Current Assignee: Sony Semiconductor Solutions Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Michael Best & Friedrich LLP
- Priority: JP2015-179019 20150911
- International Application: PCT/JP2016/073817 WO 20160815
- International Announcement: WO2017/043254 WO 20170316
- Main IPC: H03L7/00
- IPC: H03L7/00 ; H03L7/083 ; H03L7/08 ; H03L7/081 ; H03L7/087 ; H03L7/07 ; H03L7/099 ; H03L7/091

Abstract:
A phase-locked loop of the disclosure includes a detector, an oscillator, an adjuster, and a controller. The detector detects a transition of an input clock signal. The oscillator generates a clock signal having a frequency corresponding to a first control signal, and changes a phase of the clock signal on a basis of a detection result in the detector. The adjuster adjusts a phase difference between a phase of the input clock signal and the phase of the clock signal depending on a second control signal. The controller compares the phase of the input clock signal and the phase of the clock signal at a plurality of comparison timings, and generates the first control signal and the second control signal on a basis of a result of the comparison.
Public/Granted literature
- US20180234098A1 PHASE-LOCKED LOOP, PHASE-LOCKING METHOD, AND COMMUNICATION UNIT Public/Granted day:2018-08-16
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